1. Field of the Invention
The present invention relates to semiconductor devices and fabrication methods thereof and, more particularly, to semiconductor devices having a contact window providing low contact resistance and high reliability and fabrication methods thereof
2. Description of the Related Art
Multilevel interconnection in a semiconductor device is important for achieving higher device density and performance. Especially, structures of contact windows and fabrication method for forming the contact windows are essential for forming the multilevel interconnection. The contact windows electrically connect a wiring layer to a semiconductor substrate or connect a wiring layer to another wiring layer. With increased device density, a depth of the contact window tends to be deeper and its width tends to be narrower. The narrow width of the contact window leads to problems such as a small contact area and, as a result, high contact resistance.
With increased device density, a space between conductive patterns also tends to be closer and closer. This tendency makes the width of the contact window more decreased. This is because the contact window is generally formed to pass through a dielectric material between the conductive patterns. This will be further described below with reference to drawings.
FIGS. 1 to 4 are cross sectional views illustrating a process for forming a contact window in a semiconductor device in accordance with a Korean Patent Laid-open Publication No.99-46930.
Referring to FIGS. 1 and 2, a lower dielectric layer 5, conductive patterns 7 and an upper dielectric layer 9 are formed in sequence on a semiconductor substrate 1 having an impurity active region 3. The impurity active region 3 has a predetermined width 13. The lower dielectric layer 5 has a higher wet etch rate than a wet etch rate of the upper dielectric layer 9 for a selected oxide etching solution such as hydrofluoric acid (HF) solution. The lower dielectric layer 5 is formed of a borophosphosilicate glass (BPSG) layer or a spin-on-glass (SOG) layer. The upper dielectric layer 9 is formed of an undoped silicate glass (USG) layer or a high density plasma (HDP) oxide layer. On the upper dielectric layer 9, a photoresist pattern 11 having an opening is formed to define a contact window area. The upper dielectric layer 9 and the lower dielectric layer 5 are partially removed by a dry etching process using the photoresist pattern 11 as an etch mask. As a result, a contact window 19 is formed to expose the impurity active region 3. At this time, the conductive patterns 7 should not be exposed by the contact window 19 as shown in FIG. 2. Therefore, the width 21 of the contact window 19 should be narrower than the spacing 15 between the conductive patterns 7.
The exposed surface 22 of the impurity active region 3 is severely damaged due to the dry etching process during formation of the contact window 19. Accordingly, the etching damage may increase contact resistance and junction leakage current.
Referring to FIG. 3, the resultant structure is dipped into the selected oxide etching solution to form a final contact window 19xe2x80x2. With this wet etching, the upper dielectric layer 9 is etched to a lesser extent of a selected width 20 in a lateral direction; the lower dielectric layer 5 is etched to greater extent in the lateral direction. Consequently, the final contact window 19xe2x80x2 has a wider width 21xe2x80x2 in a lower region than the width in an upper region. Therefore, an exposed surface area of the impurity active region 3 is increased by the wet etching, as compared with an exposed surface area formed immediately after the dry etching. Referring to FIG. 4, the photoresist pattern 11 is removed. Then, a wiring material 24 is formed on the resultant structure to fill the contact window 19xe2x80x2.
In the prior art, the dry etching exposes the semiconductor substrate 1. If the dry etching is overdone, it may cause a surface damage 22 (See FIG. 2) of the impurity active region 3. Therefore, the dry etching should be controlled with high accuracy to prevent the damage. This dry etching damage causes serious problems such as high contact resistance and high junction leakage current in a semiconductor device.
The contact window 19 should not expose the conductive patterns 7 to insure electrical isolation therebetween. Therefore, a width 17 of the opening of the photoresist pattern 11 and a width 21 of the contact window 19 should not be increased greater than a distance 15 between the conductive patterns 7. In other words, the shorter the spacing between the conductive patterns 7 is, the narrower the width of the contact window 19 is, as described above.
The wet etching also should be controlled with high accuracy, because a distance 26 between the wiring material 24 and the conductive patterns 7 needs to be properly maintained. Assume that the wet etching is overdone and the lower dielectric layer 5 is excessively etched in the lateral direction, and, as a result, the contact window 19xe2x80x2 exposes a bottom side of the conductive patterns 7. This can result in an undesirable electrical connection between the wiring material 24 and the conductive patterns 7. Therefore, in the prior art, the width 21xe2x80x2 in a lower region of the final contact window 19xe2x80x2 cannot be greater than the spacing between the conductive patterns 7. Thus, a contact area between the wiring layer and the conductive patterns 7 is limited by the spacing between the conductive patterns 7. Accordingly, it is difficult to reduce contact resistance.
According to the prior art, the dry and the wet etching should be performed very carefully. That is to say, it is very difficult to maintain the high accuracy necessary to avoid above-mentioned problems during the dry and wet etching.
It is, therefore, an object of the present invention to provide a method for forming a contact window without dry etching damage in a semiconductor substrate. Another object of the present invention is to provide a method for forming a contact window that maximizes a contact area and improves electrical isolation characteristic with neighboring conductive patterns simultaneously.
Another object of the present invention is to provide a structure for a contact window that improves the contact resistance and junction leakage current characteristics as well as the electrical isolation characteristic with neighboring conductive patterns.
According to one aspect of the invention, a method of forming a contact window is provided. This method comprises forming a lower dielectric layer and an upper dielectric layer in sequence on a semiconductor substrate. The lower dielectric layer has a higher isotropic etch rate than an isotropic etch rate of the upper dielectric layer for a selected isotropic etching condition. The upper dielectric layer and the lower dielectric layer are etched by an anisotropic etching to form a trench not exposing the semiconductor substrate.
Thus, it is possible to prevent the semiconductor substrate from being damaged by the anisotropic etching. A sidewall of the trench is substantially perpendicular to the substrate. The resultant structure is subject to a wet etching using the selected isotropic etching condition to expose the substrate. A difference in the etch rates of the upper and the lower dielectric layers makes a contact window having a wider width in a lower region than a width in a upper region. For example, the lower dielectric layer is a layer selected from the group consisting of a borophosphosilicate glass (BPSG) layer, a spin-on-glass (SOG) layer and O3-TEOS layer. The upper dielectric layer is a layer selected from the group consisting of an undoped silicate glass (USG) layer, a high density plasma (HDP) oxide layer and O2-TEOS layer. The lower dielectric layer may be a TEOS layer. The TEOS layer is formed by a process in which a flow rate of O3 gas is decreased and a flow rate of O2 gas is increased from an initial stage to an ending stage of the process. In addition, before the wet etching, a polymer with a thickness of 100-500xc3x85 or a spacer formed of a material selected from the group consisting of polycrystalline silicon, silicon nitride and silicon oxynitride may be formed on the sidewall of the trench.
According to another aspect of the present invention, a semiconductor device is provided. The semiconductor device comprises a lower dielectric layer and an upper dielectric layer formed on a substrate, and a contact window formed through the dielectric layers. The contact window includes an upper contact window and a lower contact window extended from the upper contact window to the substrate. The upper contact window has a sidewall substantially perpendicular to the substrate. However, the lower contact window has a sloped sidewall profile such that a width of the lower contact window becomes wider and wider along the downward direction. The lower dielectric layer is a TEOS layer. The TEOS layer is formed by a process in which a flow rate of O3 gas is decreased and a flow rate of O2 gas is increased from an initial stage to an ending stage of the process. The semiconductor device also has a plurality of conductive patterns intervening between the upper dielectric layer and the lower dielectric layer. The plurality of conductive patterns is spaced apart from the contact window. A bottommost width of the contact window may be wider than a space between one conductive pattern and the other conductive pattern.
According to another aspect of the present invention, a semiconductor device has a first dielectric layer, a second dielectric layer and an upper dielectric layer sequentially stacked on a substrate, and has a contact window penetrating the dielectric layers. The semiconductor device also has a plurality of conductive patterns intervening between the first dielectric layer and the second dielectric layer. The plurality of conductive patterns is spaced apart from the contact window. The contact window in the first dielectric layer is wider than that in the second dielectric layer and the upper dielectric layer. A bottommost width of the contact window may be wider than a space between one conductive pattern and the other conductive pattern.
Accordingly, it is possible to maximize a contact area between a conductive material filling the contact window and the substrate, resulting in a reduction of the contact resistance. In addition, the semiconductor device may further comprise a spacer on the sidewall of the upper contact window. The spacer is formed of a material selected from the group consisting of polycrystalline silicon, silicon nitride and silicon oxynitride.